By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
This monograph relies at the 3rd author's lectures on machine structure, given in the summertime semester 2013 at Saarland college, Germany. It encompasses a gate point building of a multi-core computer with pipelined MIPS processor cores and a sequentially constant shared memory.
The publication includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache established sequentially constant shared reminiscence. This opens how you can the formal verification of synthesizable for multi-core processors within the future.
Constructions are in a gate point version and therefore deterministic. by contrast the reference versions opposed to which correctness is proven are nondeterministic. the improvement of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.
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Additional info for A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof
Then e (a) = 1 would by hypothesis imply the contradiction e(a) = 1. Because in Boolean algebra e (a) ∈ B we conclude e (a) = 0. Thus, we have e(a) = e (a) for all a ∈ Bn . 1 Identities In this section we provide a list of useful identities of Boolean algebra. 6 Boolean Algebra 25 Table 4. Verifying the ﬁrst of de Morgan’s laws x1 0 0 1 1 • x1 ∧ x2 0 0 0 1 x2 0 1 0 1 x1 ∧ x2 1 1 1 0 x1 1 1 0 0 x2 1 0 1 0 x1 ∨ x2 1 1 1 0 De Morgan’s laws: x1 ∧ x2 ≡ x1 ∨ x2 x1 ∨ x2 ≡ x1 ∧ x2 Each of these identities can be proven in a simple brute force way: if the identity has n variables, then for each of the 2n possible substitutions of the variables the left and right hand sides of the identities are evaluated with the help of Table 3.
Detailed timing of the reset signal ρ to σ after regular clocking, and ii) the entire time interval if there was a violation of the stability conditions of any kind. Usually, a physical register will settle in this situation quickly into an unknown logical value, but in rare occasions the register can “hang” at a voltage level not recognized as 0 or 1 for a long time. This is called ringing or metastability. Formally, we deﬁne the register semantics of the detailed hardware model in the following way: ⎧ a[i] reset(t) ⎪ ⎪ ⎪ ⎪ ⎪ x[i]in(e(c)) t ∈ [e(c) + σ, e(c + 1) + ρ] ∧ stable(x[i]in, c) ⎪ ⎪ ⎪ ⎨ ∧ stable(x[i]ce, c) ∧ x[i]ce(e(c)) ∧ ¬reset(t) x[i](t) = ⎪ x[i](e(c)) t ∈ (e(c) + ρ, e(c + 1) + ρ] ∧ stable(x[i]ce, c) ⎪ ⎪ ⎪ ⎪ ⎪ ∧ ¬x[i]ce(e(c)) ∧ ¬reset(t) ⎪ ⎪ ⎩ Ω otherwise .
2. This is basically the same collection of circuits as presented in . In Sect. , in [10,14]. Working out the proof sketch from , we formalize timing analysis and show by induction on depth that, with proper timing analysis, the detailed model is simulated by the digital model. This justiﬁes the use of the digital model as long as we use only gates and registers. In the very simple Sect. R of hardware conﬁgurations h. As we aim at the construction of memory systems, we extend in Sect. 5 both circuit models with open collector drivers, tristate drivers, buses, and a model of main memory.
A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul