By Himanshu Bhatnagar
Complex ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment version describes the complicated techniques and methods used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the complete ASIC layout circulation technique detailed for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this publication is on real-time program of Synopsys instruments, used to wrestle numerous difficulties visible at VDSM geometries. Readers might be uncovered to a good layout method for dealing with advanced, sub-micron ASIC designs. importance is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to format, actual synthesis, and static timing research. At each one step, difficulties relating to every one section of the layout move are pointed out, with recommendations and work-around defined intimately. furthermore, an important matters on the topic of format, inclusive of clock tree synthesis and back-end integration (links to format) also are mentioned at size. in addition, the publication comprises in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding types, designated in the direction of optimum synthesis resolution. aim audiences for this e-book are practising ASIC layout engineers and masters point scholars project complicated VLSI classes on ASIC chip layout and DFT options.
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Additional resources for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime
In addition, if a hierarchical place and route has been performed, the physical placement location of cells in the PDEF format should also be generated. 1 Post-Layout Static Timing Analysis using PrimeTime The first step after layout is to perform static timing on the design, using the actual delays. Similar to post-placement, the post-route timing analysis uses the same commands, except that this time the actual delays are back annotated to the design. Predominantly, the timing of the design is dependent upon clock latency and skew.
This constraint file in SDF format specifies the timing between each group of logic that the layout tool uses, in order to perform the timing driven placement of cells. In the post-layout mode, the actual extracted delays are back annotated to PrimeTime to provide realistic delay calculation. These delays consist of the net capacitances and interconnect RC delays. Similar to synthesis, static timing analysis is also an iterative process. It is closely linked with the placement and routing of the chip.
The estimated delays are back annotated to PrimeTime for analysis, and only when the timing is considered satisfactory, the remaining process is allowed to proceed. Detailed routing is the final step that is performed by the layout tool. After detailed route is complete, the real timing delays of the chip are extracted, and plugged into PrimeTime for analysis. These steps are iterative and depend on the timing margins of the design. If the design fails timing requirements, post-layout optimization is performed on the design before undergoing another iteration of layout.
Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime by Himanshu Bhatnagar